¾ÂÄŹâÀì ÅÅ»ÒÀ©¸æ¹©³Ø²Ê
MIRS0205 CPU¥Ü¡¼¥ÉÀ½Â¤»ÅÍͽñ
MIR0205-ELEC-0601
²þÄûµÏ¿
ÈÇ¿ô
ºîÀ®Æü
ºîÀ®¼Ô
¾µÇ§
²þÄûÆâÍÆ
A01
2003.7.4
Êö»³
¹âº¬ß·
½éÈÇ
Fig.1 CPU¥Ü¡¼¥É (cpu1.jpg)
³Æ¥³¥Í¥¯¥¿¤ÎÀܳ¾ì½ê
ÈÖ¹æ
Àܳ¾ì½ê
¥³¥Í¥¯¥¿Ì¾¾Î
È÷¹Í
¡
Flash Disk
CPU_IDE
¢
¥×¥ê¥ó¥¿¥Ý¡¼¥È
FPGA¤«¤é¤Î¥À¥¦¥ó¥í¡¼¥É¥±¡¼¥Ö¥ë¤Ï³ô¼°²ñ¼Ò¡¡¥¢¥Æ¥ê¥Ã¥¯¤ÎMB-CABLE¤ò»ÈÍѤ¹¤ë¡£
£
ETHERNET
CPU_UTP
¤
¥Æ¥ó¥¡¼
CPU_KB
¥
Back Plane